How does cache coherence work in multiprocessors?

TL;DR

Cache coherence ensures that multiple caches see a unified value for shared data, preventing inconsistent views after updates. The system uses hardware protocols like snooping or directory based approaches, with cache line states such as modified, shared, invalid, and optional exclusive, owned, forward. These mechanisms coordinate reads and writes across cores.

Transcript

hello everyone and welcome back in this session we are going to look into multiprocessor systems and in multiprocessor system there is a problem associated with it that is known as cache coherence problem and as a solution to this problem we propose cache coherency protocols so in today's session we are first going to state the cache coherence prob... Read More

Key Insights

• Cache coherence addresses the problem of inconsistent shared data across multiple private caches in a multi core system.
• Cache lines in caches can be in states like modified, shared, and invalid, with additional states exclusive owned and forward depending on protocol.
• Snooping based protocols rely on bus broadcasts where caches monitor traffic to maintain coherence.
• Write update versus write invalidate are two fundamental approaches in snooping protocols, differing in whether other caches are updated or invalidated.
• Write through and write back are two strategies that determine when data is written to memory or cache, affecting coherence traffic.
• Directory based protocols centralize coherence information in a directory and use point to point interconnects rather than a shared bus.
• Exclusive and forward states indicate that a cache line is owned by a single cache or forwarded to others to assist in updates.
• Hardware based cache coherence protocols outperform software based schemes and are central to maintaining coherence in multiprocessor systems.
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Questions & Answers

Q: What is cache coherence in multiprocessor systems?

Cache coherence is the uniformity of shared resource data stored in multiple private caches across processors. It ensures that when one processor updates a shared data item, other processors see the updated value and do not operate on stale copies. The problem arises when independent caches hold different values for the same data item, leading to inconsistent program behavior. Coherence is maintained by protocols that coordinate how and when caches invalidate, update, or forward data, preserving a single coherent view of memory across all cores.

Q: What are the common cache line states used in coherence protocols?

Cache lines are tracked with specific states to manage coherence. Modified means the line has been changed by a processor and is not in sync with memory. Shared means the line is unmodified and can appear in several caches. Invalid means the line has been invalidated due to another processor's update. Additional states include Exclusive, Owned, and Forward, which indicate unique ownership, responsibility for serving reads, and forwarding updates to other caches, respectively.

Q: What is the difference between snooping and directory based protocols?

Snooping protocols monitor a shared bus and broadcast requests so all caches can observe and react, using strategies like write update or write invalidate. Directory based protocols use a central directory to track data presence and ownership, connecting caches via point-to-point networks rather than a common bus, which scales better for larger multiprocessor systems.

Q: What are write update and write invalidate strategies?

In write update, when a cache line becomes modified, all other caches that shared the line are updated to reflect the new value. In write invalidate, other caches invalidate their copies so only one cache holds the latest version, forcing others to fetch or reoccupy the data when needed. These strategies trade coherence traffic for latency and bandwidth.

Q: What is the role of the forward state in coherence protocols?

The forward state designates a cache that can forward updated data to other caches. When a shared block is updated, the cache in the forward state is responsible for distributing the new value to the others, reducing latency for subsequent reads by other processors and helping maintain a coherent view across the system.

Q: What does the exclusive state signify in a cache line?

Exclusive state means the cache line is present only in the current cache and matches the main memory, making it eligible to transition to a shared state if other processors request access. This state implies that the line can be changed to shared without immediate invalidation, enabling efficient transitions during read requests from other processors.

Q: Why are cache coherence protocols important for performance?

Coherence protocols are essential because they preserve data consistency without requiring consistent global memory access, which would be costly. They improve performance by allowing private caches to operate efficiently while ensuring that shared data remains coherent across all cores, balancing traffic between caches and memory and avoiding stale reads.

Q: How do modified, shared, and invalid states interact during updates?

When a processor modifies a line in its cache, the state typically moves to Modified, and other caches holding the same line may be invalidated or updated depending on the protocol. If another processor reads the data, it may fetch the updated value from memory or from the forward or owner cache, potentially transitioning its copy to Shared. This coordination ensures all caches converge to the latest value.

Summary & Key Takeaways

• Cache coherence is the uniformity of shared data across private caches in a multiprocessor system, preventing inconsistent values when multiple processors access the same data. The talk covers hardware based protocols, states, and two major protocol families, snooping and directory based, including read and write behaviors.

• Snooping protocols broadcast on a bus to keep caches in sync, with strategies like write update or write invalidate, and variations such as write through or write back. Directory based protocols use centralized tracking to coordinate data ownership and invalidate or update caches as needed.

• Key concepts include private L1/L2 caches, a shared L3 and main memory, and the need to maintain coherence when cores modify a shared variable, guided by states and protocol rules.