How Does Direct Cache Memory Mapping Work?

TL;DR

Direct cache mapping assigns each main-memory block to one specific cache line using a strict, repeating pattern. A physical address is divided into tag, line-number, and block-offset fields: the line bits select the cache line, the tag identifies which eligible block is currently stored there, and the offset selects a word within that block.

Transcript

hello everyone welcome back in our previous session we learned about the cashier memory from this session onwards we will focus on different cache memory mapping techniques starting with the direct memory mapping so gear up and let's get to learning so as you can see in here this is the conceptual block diagram of the secondary memory and this is a... Read More

Key Insights

• Direct cache mapping is a strict placement method in which each main-memory block can map to only one designated cache line. When the available lines have all been assigned, later blocks repeat the same line sequence in a round-robin manner.
• Main memory is organized into blocks, while cache memory is organized into lines. A cache line and a main-memory block must have the same size so that the contents of a complete block can occupy its assigned line.
• A word is the smallest addressable memory unit in the example. In byte-addressable memory, each word has a size of one byte, and the physical address identifies a particular word within the physical address space.
• The example main memory contains 64 words divided into blocks of four words each. This organization produces 16 blocks, numbered from 0 through 15, with each block holding a consecutive group of four memory words.
• A six-bit physical address is sufficient to address the 64 words in the example. Before cache-line selection is considered, its four most significant bits identify the block and its two least significant bits identify the word within that block.
• The example cache contains 16 words divided into four lines of four words each. Because four lines must be distinguished, two bits are used as the line number that determines the destination cache line.
• The cache-line assignment is determined by the least significant bits of the block number. Blocks 0, 4, 8, and 12 map to line 0, while corresponding repeating groups map to lines 1, 2, and 3.
• Tag bits identify which competing memory block is currently present in a selected cache line. For blocks 3, 7, 11, and 15, which all map to line 3, the tags are 00, 01, 10, and 11 respectively.

Questions & Answers

Q: How does direct cache memory mapping work?

Direct cache memory mapping assigns every main-memory block to one predetermined cache line. The assignments repeat in a round-robin pattern after every cache line has been used. In the example, blocks 0, 4, 8, and 12 all map to line 0. This creates a many-to-one relationship because several memory blocks compete for the same cache line.

Q: How are main memory and cache memory organized?

Main memory is conceptually divided into equal-sized blocks, and cache memory is divided into equal-sized lines. Each line has the same size as each block, allowing an entire main-memory block to occupy one cache line. These divisions are conceptual tools for understanding memory organization rather than physical lines drawn on cache or RAM hardware.

Q: How is a physical address split in direct mapping?

A physical address is separated into a block or line offset, a line number, and tag bits. The least significant offset bits select a word inside the chosen block or cache line. The line-number bits specify the cache line to which the block maps. The remaining most significant bits form the tag used to identify the resident block.

Q: What is the purpose of the block offset?

The block offset identifies a particular word within a main-memory block or cache line. In the example, each block and line contains four words, so the two least significant physical-address bits serve as the offset. The patterns 00, 01, 10, and 11 select the zeroth, first, second, and third words respectively.

Q: What do the line-number bits identify?

The line-number bits identify the cache line assigned to a main-memory block. In the example cache, there are four lines, so two bits distinguish lines 0 through 3. These bits come from the least significant portion of the block number and enforce the repeating placement pattern used by direct cache mapping.

Q: Why are tag bits needed in direct cache mapping?

Tag bits are needed because several main-memory blocks can map to the same cache line. The line number alone identifies only the destination line, not which eligible block currently occupies it. The tag distinguishes among those competing blocks. For line 3, blocks 3, 7, 11, and 15 have different tag patterns.

Q: How many address bits are required for the example memory?

The example main memory contains 64 addressable words, numbered from 0 through 63, so six physical-address bits are required. The four most significant bits initially identify one of the 16 blocks, and the two least significant bits identify one of four words within the selected block. Cache mapping further separates the block-number field into tag and line-number bits.

Q: Why is the technique called direct mapping?

The technique is called direct mapping because every main-memory block maps directly to a specific cache line under a strict assignment rule. A block cannot be placed in any arbitrary line. Once the sequence reaches the final cache line, later blocks repeat the sequence, causing multiple blocks to share the same designated line at different times.

Summary & Key Takeaways

• Programs reside permanently in secondary storage and become processes during execution. Processes are divided into equal-sized pages, while main memory is divided into equal-sized frames. Cache organization uses a related structure: main memory is divided into blocks, cache is divided into lines, and every cache line has the same size as a memory block.

• In the example, main memory contains 64 words and each block contains four words, producing 16 memory blocks. Addressing any of the 64 words requires six physical-address bits. The four most significant bits identify a memory block, while the two least significant bits select one of the four words within that block.

• A 16-word cache with four-word lines contains four cache lines. Direct mapping assigns memory blocks to these lines in a repeating round-robin pattern. The physical address is therefore interpreted using a block offset, a line number, and a tag. The tag distinguishes blocks that compete for the same cache line.