[Eng Sub] Intel Foveros

TL;DR

Intel Foveros is a 3D packaging technology enhancing chip performance.

Transcript

Hello everyone, welcome to Semicon Talk! Today’s topic is Intel Foveros. Let’s talk about it.   Foveros is a die to die connection 3D packaging technology using active interposer with TSV and it is developed by Intel.    Foveros is a greek word and its meaning is “Unique and Special” based on explanation from Intel.  Foveros uses active Si interp... Read More

Key Insights

• Foveros is a 3D packaging technology developed by Intel, using active interposers with TSV to connect dies, offering improved performance and efficiency.
• The technology differs from 2.5D packaging by using an active Si interposer with integrated circuits, unlike the passive Si interposer in 2.5D.
• Foveros enhances chip performance by providing a small form factor, high bandwidth, reduced latency, and power efficiency through short die-to-die interconnections.
• The first product using Foveros was the Intel Core i5-L16G7, codenamed Lakefield, featuring a package-on-package structure and a 12x12mm size.
• Lakefield used micro bumps and TSV for die connection, with the top compute die using 10nm technology and the bottom base die using 22nm technology.
• Foveros has evolved through multiple generations, with Foveros Omni and Foveros Direct offering further improvements in bump pitch and connection technology.
• Foveros Omni uses copper columns to enhance signal integrity, while Foveros Direct employs Cu to Cu bonding, eliminating micro bumps for tighter interconnections.
• Foveros technology has been applied in products like the Samsung Galaxy Book S, Aurora Supercomputer, and is planned for Intel Meteor Lake in 2023.

Questions & Answers

Q: What is Intel Foveros technology?

Intel Foveros is a 3D packaging technology that connects dies using active interposers with through-silicon vias (TSV). This technology enhances chip performance by providing a small form factor, high bandwidth, reduced latency, and improved power efficiency through short die-to-die interconnections. It differs from 2.5D packaging by using an active Si interposer with integrated circuits.

Q: How does Foveros technology differ from 2.5D packaging?

Foveros technology differs from 2.5D packaging primarily through its use of an active Si interposer instead of a passive one. The active interposer in Foveros includes integrated circuit structures, whereas the passive interposer in 2.5D only provides electrical interconnections. This distinction allows Foveros to offer enhanced performance, including higher bandwidth and reduced latency.

Q: What was the first product to use Foveros technology?

The first product to use Foveros technology was the Intel Core i5-L16G7, codenamed Lakefield, launched in 2019. Lakefield features a package-on-package structure with a 12x12mm size and 1mm thickness. It uses micro bumps and TSV to connect the top compute die, which employs 10nm technology, and the bottom base die, utilizing 22nm technology.

Q: What are the key components of the Lakefield processor using Foveros technology?

The Lakefield processor using Foveros technology consists of a top compute die and a bottom base die. The top compute die, manufactured with 10nm technology, includes the compute core, graphics, and memory controller. The bottom base die, made with 22nm technology, contains peripheral components such as the security controller, USB ports, and PCIe lanes. These dies are connected using micro bumps and TSV.

Q: What are Foveros Omni and Foveros Direct?

Foveros Omni and Foveros Direct are advanced variants of Intel's Foveros technology. Foveros Omni, the 3rd generation, introduces copper columns to enhance signal integrity and reduce TSV penalties. Foveros Direct, the 4th generation, employs Cu to Cu bonding technology, eliminating micro bumps for tighter interconnections with a bonding pitch of less than 10um, enabling over 10,000 interconnections per mm².

Q: How does Foveros Direct improve upon previous generations?

Foveros Direct improves upon previous generations by using Cu to Cu bonding technology, which eliminates the need for micro bumps. This allows for a bonding pitch of less than 10um, enabling over 10,000 interconnections per mm². This advancement provides tighter interconnections, enhancing performance by reducing latency and increasing bandwidth, making it suitable for high-performance computing applications.

Q: What applications have utilized Foveros technology?

Foveros technology has been utilized in several applications, including the Samsung Galaxy Book S laptop, which featured the Lakefield processor. It is also used in the Ponte Vecchio GPU for supercomputers, such as the Aurora supercomputer. Additionally, Foveros technology is planned for use in Intel Meteor Lake processors for personal computers in 2023, leveraging its advanced packaging capabilities.

Q: What are the benefits of using Foveros technology in supercomputers?

Using Foveros technology in supercomputers offers several benefits, including enhanced performance through high bandwidth and reduced latency due to short die-to-die interconnections. The technology's small form factor and power efficiency are crucial for managing the high computational demands of supercomputers. Foveros also supports advanced interconnections, as seen in the Ponte Vecchio GPU, used in the Aurora supercomputer, enabling efficient data processing and communication.

Summary & Key Takeaways

• Intel's Foveros technology is a 3D packaging solution that uses active interposers with TSV to improve chip performance. It offers a small form factor, high bandwidth, and power efficiency by facilitating short die-to-die connections.

• The technology was first implemented in the Intel Core i5-L16G7, known as Lakefield, which features a package-on-package structure with a 12x12mm size. It uses micro bumps and TSV to connect a 10nm top compute die and a 22nm bottom base die.

• Foveros has evolved through several generations, with Foveros Omni and Foveros Direct providing further advancements. These include copper columns for signal integrity and Cu to Cu bonding for tighter interconnections, making it suitable for high-performance applications like supercomputers.