[Eng Sub] TSMC SOIC

TL;DR

TSMC SoIC uses Cu pads for high-density chip interconnections.

Transcript

Hello everyone, welcome to Semicon Talk! Today’s topic is TSMC SoIC. Let’s talk about it! TSMC SoIC is the technology name coined by TSMC and it means System on Integrated Chips. It is one of technologies of TSMC using fab technology and fab technology is also called as Front End technology. FE 3D means Front End 3D. BE 3D means Back End 3D. TS... Read More

Key Insights

• TSMC SoIC stands for System on Integrated Chips and is a technology developed by TSMC for chip interconnections using fab technology instead of traditional packaging methods.
• The technology employs Cu pads instead of microbumps, allowing for smaller interconnection pitches and significantly increasing the number of I/Os per square millimeter.
• The process flow of TSMC SoIC involves four main steps: Chemical Mechanical Polishing (CMP), Surface Activation by plasma, Chip to Chip Bonding, and Annealing.
• Cu to Cu hybrid bonding is a crucial part of the TSMC SoIC process, enabling metal bonding at high temperatures and electrical connections between chips.
• TSMC SoIC technology allows for a drastic increase in bump density, which translates to faster data processing performance due to the higher number of I/Os.
• Key machine suppliers for Cu to Cu hybrid bonding technology include EVG, SUSS MicroTec, ASM Pacific, Besi, and Applied Materials.
• The technology has practical applications in products like Sony image sensors and AMD's 3D V-Cache, indicating its potential for high-performance computing.
• The use of TSMC SoIC technology in AMD's 3D V-Cache showcases its development for gaming and future applications in high-performance computing.

Questions & Answers

Q: What is TSMC SoIC?

TSMC SoIC stands for System on Integrated Chips, a technology developed by TSMC to enable chip interconnections using fab technology. It replaces traditional packaging methods by using Cu pads instead of microbumps, allowing for smaller interconnection pitches and significantly increasing the number of I/Os per square millimeter.

Q: How does TSMC SoIC increase I/O density?

TSMC SoIC increases I/O density by using Cu pads instead of microbumps, which allows for much smaller interconnection pitches. This results in a higher number of I/Os per square millimeter, enabling faster data processing performance. For example, a 10um pitch can achieve 10,000 I/O per mm2, significantly enhancing chip performance.

Q: What are the main steps in the TSMC SoIC process?

The TSMC SoIC process involves four main steps: Chemical Mechanical Polishing (CMP) to prepare the bonding surface, Surface Activation by plasma to increase bonding energy, Chip to Chip Bonding at room temperature for dielectric material bonding, and Annealing for Cu to Cu metal bonding at high temperature, creating electrical connections.

Q: What is Cu to Cu hybrid bonding?

Cu to Cu hybrid bonding is a process used in TSMC SoIC technology that involves bonding Cu pads at high temperatures to create electrical connections between chips. This method allows for increased bump density and faster data processing performance. It is a key component of the TSMC SoIC process, enabling high-density chip interconnections.

Q: Who are the key machine suppliers for Cu to Cu hybrid bonding?

The key machine suppliers for Cu to Cu hybrid bonding technology include EVG, SUSS MicroTec, ASM Pacific, Besi, and Applied Materials. These companies provide the necessary equipment and technology to facilitate the Cu to Cu hybrid bonding process, which is essential for the TSMC SoIC technology.

Q: What are some applications of TSMC SoIC technology?

TSMC SoIC technology is used in various applications, including Sony image sensors and AMD's 3D V-Cache. The technology enables high-density chip interconnections, making it suitable for high-performance computing and gaming applications. AMD's 3D V-Cache, for example, connects processor chips with L3 cache SRAM memory using Cu to Cu hybrid bonding.

Q: How does TSMC SoIC technology benefit data processing performance?

TSMC SoIC technology benefits data processing performance by significantly increasing bump density, which allows for more I/Os per square millimeter. This increase in I/O density translates to faster data processing speeds, as more data can be transferred simultaneously, enhancing the overall performance of electronic devices using this technology.

Q: What challenges are associated with the TSMC SoIC process?

One of the challenges associated with the TSMC SoIC process is the need for high precision alignment due to the narrow bond pitch, such as 10um. Additionally, chip surfaces must be free of particles to ensure proper bonding. The annealing process also presents challenges, as filling gaps without voids during Cu to Cu metal bonding is difficult.

Summary & Key Takeaways

• TSMC SoIC, or System on Integrated Chips, is a technology by TSMC using Cu pads instead of microbumps for chip interconnections, allowing for higher I/O density. The process involves CMP, plasma activation, chip bonding, and annealing, significantly increasing data processing performance.

• Cu to Cu hybrid bonding is central to TSMC SoIC, facilitating metal bonding at high temperatures for electrical connections. The technology is employed in products like Sony image sensors and AMD's 3D V-Cache, aimed at high-performance computing and gaming.

• TSMC SoIC technology drastically increases bump density and data processing speed. Key machine suppliers include EVG and ASM Pacific. AMD's 3D V-Cache uses this technology, connecting processor chips with L3 cache SRAM memory through Cu to Cu hybrid bonding.