8.2.4 Binary Multiplication

TL;DR

Multipliers in arithmetic and logic units are slow and large, but by making tradeoffs, they can be made smaller or faster.

Transcript

One of the biggest and slowest circuits in an arithmetic and logic unit is the multiplier. We'll start by developing a straightforward implementation and then, in the next section, look into tradeoffs to make it either smaller or faster. Here's the multiplication operation for two unsigned 4-bit operands broken down into its component operations. T... Read More

Key Insights

• 🐢 Multipliers are one of the slowest and largest circuits in arithmetic and logic units.
• 🪜 The multiplication process involves calculating partial products and adding them together.
• 🤘 Two's complement operands require additional computations for sign-extension and handling negative weights.
• 💄 The hardware costs of multiplier circuits can be reduced by optimizing the circuit layout and making tradeoffs.
• 🙅 The latency of the multiplier circuit is order N, where N is the number of columns.
• ✖️ The throughput of the multiplier circuit is 1/latency.
• 🪈 The total amount of hardware in the multiplier circuit is order N^2.

Questions & Answers

Q: Why is the multiplier circuit one of the slowest and largest circuits?

The multiplier circuit requires the computation of multiple partial products and their subsequent addition, which increases the latency and hardware requirements.

Q: How does the multiplication process work?

The multiplication process involves multiplying each digit of the multiplier with each digit of the multiplicand, and shifting the partial products to the left to reflect the increasing weight of the multiplier digits.

Q: What are the challenges when dealing with two's complement operands in multiplication?

With two's complement operands, the high-order bit has negative weight, requiring sign-extension of the partial products. Additional computations are needed to handle the subtraction of the last partial product.

Q: How can the hardware costs be reduced in multiplier circuits?

Hardware costs can be reduced by making tradeoffs, such as using NAND gates instead of AND gates for necessary complements and optimizing the circuit layout.

Summary & Key Takeaways

• Multipliers are one of the largest and slowest circuits in arithmetic and logic units.

• The process of multiplication involves breaking down the operands into digits and using multiplication tables to calculate the partial products.

• The multiplication circuit requires AND gates for forming the partial products and adder modules for adding them together.