Lets Learn Verilog with real-time Practice with Me | Logic Gates | DAY 2

Transcript

foreign courses today's task is that we need to create a module with a one input and one output that we have like aware so what's aware in in general while we know where is something like if you give something here you will get here if you give here you will get there but in verilog wire is something like a net type in verilog actually we have two ... Read More