What Is DRAM and How Does It Work?

TL;DR

Dynamic Random-Access Memory (DRAM) uses a capacitor and a MOSFET to store data, represented by voltage levels. It offers higher storage capacities than SRAM but requires periodic refreshing to prevent data loss due to leakage currents. While initial access can be slower, subsequent accesses to the same row are much faster, enhancing data retrieval efficiency.

Transcript

Well, we’ll need at least one MOSFET to serve as the access FET so we can select which bits will be affected by read and write operations. We can use a simple capacitor for storage, where the value of a stored bit is represented by voltage across the plates of the capacitor. The resulting circuit is termed a dynamic random-access memory (DRAM) cell... Read More

Key Insights

• 😒 DRAM cells use a MOSFET access transistor and a capacitor for storage, allowing for higher capacities and smaller cell sizes compared to SRAM.
• 🍽️ The capacitance of the storage capacitor can be increased by improving the dielectric layer, increasing plate area, or decreasing plate distance.
• ❓ Leakage currents from the capacitor necessitate periodic refreshing of DRAM cells to prevent data corruption.
• 🫠 DRAM read operations involve precharging the bitline, activating the wordline, and using sense amplifiers to detect voltage changes.
• 🈂️ Write operations in DRAM simply involve charging or discharging the storage capacitor through the bitline.
• 🤨 DRAM circuitry is organized with wide rows and multiple consecutive locations accessed in a single row.
• ↘️ The initial access to a row of locations in DRAM has higher latency, but subsequent accesses to the same row have low latency.

Questions & Answers

Q: How is a DRAM cell constructed?

A DRAM cell consists of a MOSFET access transistor and a capacitor for storage. The capacitor is formed in a trench within the substrate, and the wordline connects the outer plate of the capacitor to the bitline.

Q: What are the challenges associated with DRAM?

The main challenge is the leakage of stored charge from the capacitor due to small currents through the PN junction or subthreshold conduction. This requires periodic refreshing of each bit cell.

Q: How are DRAM read operations performed?

In a read operation, the bitline is precharged to an intermediate voltage, and then the wordline is activated to connect the selected cell's capacitor to the bitline. Sense amplifiers detect voltage changes on the bitline to determine the stored value.

Q: How do DRAM write operations work?

Write operations involve turning on the access FET with the wordline and charging or discharging the storage capacitor through the bitline.

Summary & Key Takeaways

• DRAM cells consist of a MOSFET and a capacitor for storage, where the voltage across the capacitor represents the stored bit value.

• The capacitance of the capacitor can be increased by improving the dielectric layer, increasing plate area, or decreasing plate distance.

• DRAM has higher capacities and smaller cell sizes compared to SRAM, but it requires refreshing to prevent data corruption due to leakage currents.