15.2.7 Worked Examples: Pipelined Beta

TL;DR

Understanding the execution of a program on a 5-stage pipelined beta processor, including stalls, annulments, and bypassing.

Transcript

For this problem, assume that you have a fully functioning 5-stage pipelined beta with full bypassing and annulment of branch delay slots as presented in lecture. This beta has been running the program shown here for a while. The actual functionality of this program is not so important for this problem, but lets just review it quickly. This program... Read More

Key Insights

• 👻 The pipelined beta processor with full bypassing and annulment allows for efficient program execution by overlapping instruction execution.
• 🥺 Dependencies between instructions can lead to data hazards and necessitate pipeline stalls.
• 🦥 Annulment of branch delay slots ensures correct execution when a branch is taken.
• 🪡 Bypass paths from different pipeline stages provide updated values to instructions, reducing the need to wait for WB stage writes.

Questions & Answers

Q: Which registers were directly read from the register file without bypassing?

Only R1 was directly read from the register file, as both the LD and ADDC instructions read from this register.

Q: In which cycle was a stall set to 1 in the pipeline?

A stall was set to 1 in cycle 1004, where the CMPEQ instruction caused a data hazard and the pipeline needed to be stalled.

Q: When was ANNUL_IF != 0?

ANNUL_IF != 0 occurred in cycle 1006 when an annulment was initiated in the IF stage to annul a branch delay slot.

Q: In which cycle was ANNUL_RF != 0?

ANNUL_RF != 0 occurred in cycle 1004 when the CMPEQ instruction stalled the RF stage, leading to a NOP being inserted in place of the CMPEQ instruction.

Q: In which cycle was ANNUL_ALU != 0?

In this particular example, an annulment in the ALU stage (ANNUL_ALU != 0) did not occur.

Q: In which cycle did a bypass come from the ALU stage?

A bypass from the ALU stage occurred in cycle 1006, where the BNE instruction read the result of the CMPEQ instruction.

Q: In which cycle did a bypass come from the MEM stage?

A bypass from the MEM stage occurred in cycle 1005 when the CMPEQ instruction read the result of the ADDC instruction.

Q: In which cycle did a bypass come from the WB stage?

A bypass from the WB stage occurred in cycle 1005 when the CMPEQ instruction read the result of the LD instruction.

Summary & Key Takeaways

• This analysis focuses on the execution of a program on a 5-stage pipelined beta processor with full bypassing and annulment of branch delay slots.

• The program initializes a register (R1), enters a loop where it loads an array element into another register (R0), increments the index (R1), and compares the element with the updated index.

• If the comparison is not equal, the program stores the index value in memory. The analysis explores how this program runs on the pipelined beta.