15.2.4 Control Hazards | Summary and Q&A

TL;DR

Control hazards occur in execution pipelines when the next instruction depends on the execution of a previous instruction, leading to stalls or incorrect speculation.

Key Insights

• 🎮 Control hazards occur when the execution of a JMP or branch instruction depends on the value in the RA register, causing stalls in the pipeline.
• 🇰🇼 Stalling the IF stage can be used to wait for necessary results, but it impacts instruction throughput.
• 👻 Speculative execution allows the pipeline to continue fetching and executing instructions, reducing the impact of control hazards.
• 🦥 Branch delay slots can reduce the negative impact of branches, but finding suitable instructions to fill the slot can be challenging.
• 💦 Branch prediction techniques often work better than branch delay slots in reducing the impact of branches.
• 👋 Altering the ISA to improve pipeline performance can have drawbacks and is not always the best solution.

Transcript

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Questions & Answers

Q: What are control hazards in execution pipelines?

Control hazards occur when the execution of JMP or branch instructions depends on the value in the RA register, causing stalls in the pipeline.

Q: How can stalling be used to deal with control hazards?

Stalling the IF stage can be used to wait for the necessary result in the RF stage, ensuring the correct instruction is fetched. However, it impacts the throughput of the pipeline.

Q: How does speculative execution help with control hazards?

Speculative execution allows the pipeline to continue fetching and executing instructions while waiting for the branch outcome. If the branch is not taken, the speculated instructions are not annulled.

Q: What are the drawbacks of using branch delay slots?

Branch delay slots can reduce the impact of branches on instruction throughput, but they require finding suitable instructions to fill the slot. Otherwise, explicit NOP instructions need to be added, increasing code size.

Summary & Key Takeaways

• Control hazards occur when the execution of a JMP or branch instruction depends on the value in the RA register, causing stalls in the pipeline.

• Stalling the instruction fetch (IF) stage can be used to wait for the necessary result in the register file (RF) stage, but it impacts instruction throughput.

• Speculative execution can be used to minimize stalls and reduce the impact of control hazards, but it requires annulment of instructions if the branch is taken.